Electronic systems and circuits have made a significant contribution towards the advancement of modern society and are utilized in a number of applications to achieve advantageous results. Electronic technologies such as digital computers, calculators, audio devices, video equipment, and telephone systems have facilitated increased productivity and reduced costs in analyzing and communicating data, ideas and trends in most areas of business, science, education and entertainment. Frequently, the electronic systems designed to provide these results include memories. However, accessing memory resources in a fast and efficient manner can involve complicated protocols.
Numerous electronic devices include processors that operate by executing software comprising a series of instructions for manipulating data in the performance of useful tasks. The instructions and associated data are typically stored in a memory. Memories usually consist of a location for storing information and a unique indicator or address. The utility a device provides often depends upon the speed and efficiency at which instructions are executed. The ability to access a memory and transfer information quickly and conveniently usually has a significant impact on information processing latency.
Traditional attempts at memory control are often very convoluted and complex. Such protocols also suffer from inefficiency and overhead in regards to latency and available bandwidth throughout the system, which can result in issues with scheduling due to unknown traffic patterns and limited resources. Such latency problems can be experienced by a host attempting to read or write information to the memory. There are a number of applications (e.g., real time applications) where processing time is critical and extended latency in retrieving or writing information to a memory can have detrimental impacts on performance and user experience. For example, in real time applications extended latency can cause jumpy presentations.
Information is typically written by a program operation that programs or writes a memory cell. The information is typically altered by erasing the cell and rewriting. The erase operation forces voltages onto the erase block that cause the bits to change to a logical 1 state, regardless of whether a particular bit previously was a logical 0 or logical 1. An erase is performed on a number of block bits simultaneously and there is a tendency for a cell that was previously at a logical 1 (e.g., an erased state) to be erased harder than a cell that was at a logical 0 state (e.g., programmed). After an erasure it is preferred that the state of the cells in a block are uniformly erased regardless of whether the previous state was a logical 0 or a logical 1. This uniformity of erase states assures that the eventual program operation is likely to be more successful. Uniformity of erase states can impact device endurance, data retention and the ability to discern multiple bits from a single cell.
The granularity of program operations can be performed on a bit-wise, word-wise or page wise basis, however, similar programming granularity is not available during Erase operations where erasure (to the 1 state) is accomplished during a single simultaneous block operation. Conventional approaches to performing an erase on a simultaneous block level can exacerbate latency problems due to the time it takes to condition and erase an entire block. FIG. 1 is a flow chart of a conventional erase sequence. An indication to erase is received in operation 91 and a page pre-program process involving operation 92, 93, 94 and 95 is performed. The “actual erasing” of cells waits while the pre-program process loops multiple times through pre-program operation 93 of driving memory cells to a logical value opposite of a static state. When all the pre-programming is completed, then the “actual erasing” of cells (e.g. driving the cells to a static state, etc.) is begun in operation 96 followed by soft program operation 97, verify operation 98 and end 99.